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Searching: cpu processor
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| Patent # | Description |
|---|---|
| US-1,075,4796 |
Efficient user space driver isolation by CPU page table switching Systems and methods for providing technology that enhances memory protection between different portions of the user space memory of a particular computing... |
| US-1,075,4777 |
Systems and methods for implementing coherent memory in a multiprocessor
system Data units are stored in private caches in nodes of a multiprocessor system, each node containing at feast one processor (CPU), at least one cache private to... |
| US-1,074,8237 |
Adaptive scheduling for task assignment among heterogeneous processor
cores Generally, this disclosure provides systems, devices, methods and computer readable media for adaptive scheduling of task assignment among heterogeneous... |
| US-1,074,7297 |
Application processor performing a dynamic voltage and frequency scaling
operation, computing system including... A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring,... |
| US-1,074,7280 |
Reconfigurble CPU/GPU interconnect to mitigate power/thermal throttling A method, a system and a computer program product for reconfiguring hardware network topology including graphics processor units (GPU) and central processing... |
| US-1,074,0131 |
Input-output based virtual CPU halt A hypervisor configures a plurality of halt registers, wherein each halt register of the plurality of halt registers is associated with a corresponding latency... |
| US-1,073,2923 |
Information processor, audio device, and program A desired range of an audio file is repeatedly reproduced without a need to store sound data of a predetermined period in a memory in advance and without... |
| US-1,072,5825 |
Data processing unit for stream processing A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central... |
| US-1,072,1067 |
Secure processor for multi-tenant cloud workloads A CPU package includes an encryption and decryption module disposed in a communication path between an instruction path of a processor core and a data register... |
| US-1,071,3166 |
Efficient early ordering mechanism Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to... |
| US-1,070,6496 |
Function callback mechanism between a Central Processing Unit (CPU) and an
auxiliary processor Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor... |
| US-1,070,6178 |
Data processing apparatus and access control method According to one embodiment, a data processing apparatus includes an access controller configured to control access by a CPU to a processor. The access... |
| US-1,069,1658 |
Automatically optimizing resource usage on a target database management
system to increase workload performance Loading a set of data into a target database management system (DBMS) from a source DBMS to increase workload performance and decrease resource usage is... |
| US-1,069,1495 |
Virtual processor allocation with execution guarantee The disclosure provides techniques for scheduling a jitterless workload on a virtual machine (VM) executing on a host comprising one or more pCPUs comprising a... |
| US-1,067,9315 |
Detected object tracker for a video analytics system Techniques are disclosed which provide a detected object tracker for a video analytics system. As disclosed, the detected object tracker provides a robust... |
| US-1,067,8909 |
Securely supporting a global view of system memory in a multi-processor
system Techniques for securely supporting a global view of system memory in a physical/virtual computer system comprising a plurality of physical/virtual CPUs are... |
| US-1,067,8700 |
CPU security mechanisms employing thread-specific protection domains A computer processor includes an instruction processing pipeline that interfaces to a hierarchical memory system employing an address space. The instruction... |
| US-1,067,8589 |
Leveraging directed acyclic graph (DAG) information to group tasks for
execution Embodiments for leveraging directed acyclic graph (DAG) information to group tasks for execution, by at least one processor. An Input/Output (I/O) cost for each... |
| US-1,067,3622 |
Cryptographic shader in display hardware A technique is introduced that can securely displaying decrypted images while preventing these decrypted images against an attempt to capture such. Some aspects... |
| US-1,066,4174 |
Resource allocation based on transaction processor classification A data transaction processing system including multiple transaction processors also includes a resource allocation system that characterizes the transaction... |
| US-1,065,7077 |
HyperConverged NVMF storage-NIC card A storage and communication apparatus for plugging into a server, includes a circuit board, a bus interface, a Medium Access Control (MAC) processor, one or... |
| US-1,065,7022 |
Input and output recording device and method, CPU and data read and write
operation method thereof The disclosure provides an input and output recording device and method, CPU and data read and write operation method thereof. The input and output recording... |
| US-1,062,1007 |
Execution of an instruction for performing a configuration virtual
topology change In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest... |
| US-1,062,0687 |
Hybrid power management approach Methods and apparatus to provide a hybrid power management approach are described. Some embodiments redefine the interface to Power Control Unit (PCU) allowing... |
| US-1,061,6530 |
Multipoint video conference device and controlling method thereof According to the present invention, by receiving, by a transceiver, videos from each of a plurality of clients, decoding, by a first processor, the plurality of... |
| US-1,061,3618 |
Programmable IMON accuracy in power systems To compensate for inaccuracies in reported values for current output from a voltage regulator (VR) to a processor, the VR may be tested, and a load line... |
| US-1,059,2696 |
CPU obfuscation for cloud applications A cloud deployment system is used for obfuscating CPU operation codes in a set of machines operating in a distributed computing environment. A reprogrammable... |
| US-1,059,2454 |
System-on-chip, mobile terminal, and method for operating the
system-on-chip A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit... |
| US-1,059,2281 |
Wait optimizer for recording an order of first entry into a wait mode by a
virtual central processing unit A wait optimizer circuit can be coupled to a processor to monitor an entry of a virtual CPU (vCPU) into a wait mode to acquire a ticket lock. The wait optimizer... |
| US-1,059,2275 |
System and method for swarm collaborative intelligence using dynamically
configurable proactive autonomous agents A parallel processing architecture includes a CPU, a task pool populated by the CPU, and a plurality of autonomous co-processing cells each having an agent... |
| US-1,059,2270 |
Safety hypervisor function The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system.... |
| US-1,057,9516 |
Systems and methods for providing power-efficient file system operation to
a non-volatile block memory Systems, methods, and computer programs are disclosed for providing power-efficient file system operation to a non-volatile block memory. An exemplary... |
| US-1,057,9093 |
Workload prediction based CPU frequency scaling A method comprises predicting, based on corresponding historical workload data, a change in virtual network function demand during a future workload period,... |
| US-1,057,2301 |
Extract CPU time facility An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that... |
| US-1,056,7304 |
Configuring transmission resources during storage area network migration One or more processors determine a throughput of hardware devices operatively coupled to a target Storage Area Network (SAN) prior to a SAN migration from a... |
| US-1,056,5382 |
Maintaining keys for trusted boot code Methods and apparatus are disclosed for securing executable code for execution with a processor using a trusted platform module (TPM). In one example of the... |
| US-1,056,4698 |
Method for controlling power supply in semiconductor device A method for controlling power supply in a semiconductor device including a CPU and a PLD which can hold data even in an off state is provided. The ... |
| US-1,055,2161 |
Cluster graphical processing unit (GPU) resource sharing efficiency by
directed acyclic graph (DAG) generation Embodiments for graphical processing unit (GPU) resource sharing in a computing cluster, by a processor device. Resource-specific stages are dynamically... |
| US-1,054,0194 |
Runtime GPU/CPU selection A method, computer program product, and system includes a processor(s) obtaining, during runtime, from a compiler, two versions of a data parallel loop for an... |
| US-1,053,6441 |
Thread ownership of keys for hardware-accelerated cryptography An embedded processor with a cryptographic co-processor operating in a multithreading environment, with inter-thread security for cryptography operations. A... |
| US-1,053,6322 |
Resource management for services A service control manager manages one or more services on a computing device, such as creating processes that host the services, stopping the processes that... |
| US-1,053,4935 |
Migration of trusted security attributes to a security engine co-processor A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes.... |
| US-1,053,4644 |
Method and system for a CPU-local storage mechanism Described herein are systems and methods for implementing a processor-local (e.g., a CPU-local) storage mechanism. An exemplary system includes a plurality of... |
| US-1,053,4641 |
Electronic device that uses hardware corresponding to priority level of
processor usage An electronic device includes a CPU that executes the process execution program to function as a plurality of process execution units as threads and an... |
| US-1,053,4542 |
Dynamic core allocation for consistent performance in a non-preemptive
scheduling environment Methods and systems are presented for allocating resources based on dynamic core allocation in a scheduler hierarchy of a storage system. One method includes... |
| US-1,052,8767 |
Systems, methods and apparatuses for secure storage of data using a
security-enhancing chip A computer processor and a security enhancing chip may be provided. In one aspect, the computer processor may comprise a storage for storing an encryption key,... |
| US-1,050,9138 |
System and method for discriminating between origins of vibrations in an
object and determination of contact... A system and method for accurately detecting contact between two objects in a medium comprises at least one sensor for detecting vibration of a first of the two... |
| US-1,050,6266 |
Resource aware video processor Approaches for dynamically allocating CPU cycle resources to a video encoder. A resource allocator assesses an amount of available CPU cycle resources on the... |
| US-1,050,6030 |
Balancing CPU utilization in a massively parallel processing heterogeneous
cluster A system (and associated method) includes a processor which determines a performance metric ratio of a performance metric of a second type of server relative to... |
| US-1,050,0909 |
Method for controlling a processor of an electronic enclosure mounted on a
wheel of a motor vehicle In a method for controlling a processor on a wheel, wheel operation parameters are calculated and transmitted to a CPU. A first default operating mode (standby... |
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